Robust Synchronization using the Wagging Technique

As integrated circuits technology sizes shrink, variability in process parameters, such as the threshold voltage, are expected to increase and become worse under low supply voltage (VDD). Circuit parameters, such as the propagation delay in logic gates and the resolution time from metastability in flipflops, will vary more. As a consequence, the synchronizer failure rate would be unpredictable. In this paper, we present the concepts of the conventional cascaded flip-flops synchronizer and wagging synchronizers, particularly how the wagging synchronizer can tolerate such variability. After that, based on simulation results, we show the effects of process and Vdd variability on both synchronizer circuits in terms resolution time constant, MTBF and latency. Then, we propose a control circuit to drive the clock phases of the wagging synchronizer. The control circuit tolerated 6 process variations up to 3GHz clock frequency and 1.0V VDD. Keywords; Wagging, synchronizer, MTBF, latency, resolution time constant, clock control circuit.